Flip-flops in ICs function when an input signal is maintained constant for a hold time, which is a predefined time interval after a clock input edge. If a series of flip-flops are used, a signal from one flip-flop should reach the succeeding flip-flop after the completion of the hold time of the succeeding flip-flop. Typically, in a high density flip-flop, only one port is used as either a data output or a scan output. The scan output is obtained at the data output when a scan enable SCAN is selected. A dedicated scan output is not generated on a separate port as it results in increase in the area of the flip flop.
In newer technology nodes, to meet performance goals a fast data path is required. A scan test in a scan flip-flop involves scan shift-in, capture and shift-out operation. The path on which the scan shift-in, capture and shift-out operation is implemented is called the scan-shift path. By using the same port for both the data output and the scan output, an input signal speeds up on the scan-shift path resulting in hold time violations (where the scan-shift path cannot be maintained). Hold time violations are therefore a result of the fast data paths between successive flip-flops, hence hold timing closure is a major concern for any flip-flop design.
One way to maintain the hold timing for scan shift operation is to use a delayed clock. However, it is challenging to meet performance goals on the data path as the data path requires a relatively fast clock. Buffers are used to prevent hold-time violations, but conventional methods of introducing delay using buffers are inefficient with respect to power consumption and size. Hence, there exists a need for a high-density flip-flop that can address back to back scan-shift hold issues.